1. Field of the Invention
The present invention generally relates to systems and methods for detecting defects on a wafer and generating inspection results for the wafer. Certain embodiments relate to a computer-implemented method for generating inspection results for a wafer by combining information about defects detected based on global criteria and local criteria.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Current patterned wafer defect detection methods involve scanning a wafer and making a decision regarding whether a pixel is defective or not, based on comparing the local neighborhood of the pixel with corresponding pixels in adjacent dies (or a reference die) and using methods to segment pixel populations based on noise or criticality (to yield) to select an appropriate threshold to be applied to the candidate pixel for making a defect/no defect decision. As soon as the defect is detected, it is marked for reporting to the next stage of the processing pipeline. Other methods for detection may first select a set of candidate pixels using a simpler (less computation) test followed by a more complex computation applied only to the candidates to determine the final defects. However, none of these methods use global, i.e., wafer wide criteria, to determine the defects to be reported (or not). The decision on which defects to report is based on local data only.
Current patterned wafer defect detection methods, therefore, have a number of disadvantages. For example, these methods do not simultaneously sample random and systematic defects. In addition, defects are flagged based on the inspection recipe, and the defect detection algorithm has no knowledge of global (wafer-wide phenomena) since the algorithm works on one frame at a time. Systematic defects may be separately monitored by recording a wafer level noise map. However, while the noise map may show a signature of systematic defects, defects from the location(s) where the anomalous signature is present may not have been detected by the threshold. Therefore, information about those defects may not have been stored such that it could be used for reporting or other purposes.
Accordingly, it would be advantageous to develop methods and systems for detecting defects on a wafer and generating inspection results for the wafer by “intelligent” defect sampling that takes into account both wafer-level criteria and local criteria.